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基于FPGA VHDL 的 FSK调制与解调设计

今天“宁夏李治廷”给各位大侠带来基于FPGA VHDL 的 FSK调制与解调。 一、VHDL语言 VHDL诞生于1982年。在1987年底，VHDL被IEEE和美国国防部确认为标准硬件描述语言。自IEEE公布了VHDL的标准版本，IEEE-1076（简称87版)之后，各EDA公司相继推出了自己的VHDL设计环境，或宣布 ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
TechRepublic

Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic

Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input /Output (I/O) hardware ...