EDN

pMEMS PLL Clock Generators

Integrated Device Technology, Inc., the Analog and Digital Company™ delivering essential mixed-signal semiconductor solutions, announced the world’s first low-power, multi-output PLL clock generators ...
EDN

On Semi unveils PureEdge PLL clock generators

Phoenix, Ariz. — ON Semiconductor has unveiled its PureEdge family of phase lock loop (PLL) based clock generation devices that is said to deliver 50 percent better phase jitter than competitive ...
Electronic Design

Unconventional PLL Uses BTSC Pilot To Generate Master Clock

Multichannel television sound (MTS), better known as Broadcast Television System Committee (BTSC) encoding, is used in many analog cable set-top boxes for TV. The BTSC pilot is at the same frequency ...
Design-Reuse

Pll clock IP Listing

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ... The ...
Design-Reuse

Auto Clock Generation in a SoC

This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting ...
Embedded

Dealing with PLL clock jitter in advanced processor designs: Part 3

Before we discuss the guidelines that the developer must follow when measuring TIE jitter, it is useful to also look at jitter for a much more general case in which jitter is not assumed to be ...