J-LINK REDUCES JTAG DEBUG PINCOUNT FROM 5 to 1! Pittsford, New York—Traditional JTAG boundary-scan testing normally takes up 5 valuable pins on an i.c., requires 5 resistors, and increases chip power.

风河系统公司（Wind River）宣布推出Wind River Workbench On-Chip Debugging 3.1.1，将这套综合性开发工具的支持平台拓展到Freescale、Intel和RMI处理器。 风河系统公司（Wind River）宣布推出Wind River Workbench On-Chip Debugging ...

Anyone who enjoys building electronic projects may find the new IDAP-Link debug JTag Probe created by I-SYST worth more investigation, as well as helpful building electronic projects. The small ...

Recently I started to evaluate a development kit that cost about $US 180. Taking the kit beyond a basic demonstration, though, required using a “JTAG” programming ...

The Joint Test Action Group (JTAG) was formed in mid 1980s to develop a method of verifying designs and testing printed circuit boards after manufacture. Prior to the development of JTAG, testing and ...

8051 instruction set compatible CPU soft core includes on-chip, real-time monitoring and debug capability, and is designed for implementation in Actel ProASICPLUS* re-programmable FPGAs PLANO, Texas, ...

Electronic enthusiasts and Raspberry Pi users may be interested in a new JTAG debugger board called Tap-Hat which has been created by the team at eCosCentric. The TAP-HAT has been designed to provide ...

JTAG debuggers tend to be large, fast, and expensive, or cheap and slow. The new crop of USB-based JTAG debuggers is cutting the cost while keeping the performance high. I recently had a chance to ...

Designed for JTAG and background debug mode (BDM) debugging, the usbDemon USB device features an application programming interface that is fully compatible with industry-standard software debuggers, ...