EDN

Take scan test out of the critical path

Integrated circuit complexity and integration continuously advances, posing challenges to the development process. Market profitability, however, demands that products be designed and produced as fast ...
EDN

Decreasing Cost-of-Test with Automatic Test-Pattern Generation

Success in the electronics business hinges on producing high-quality products and using the most cost-effective methods to do so. As the number of devices on ICs continues to double every 18 to 24 ...
Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Electronic Design

TetraMAX II shortens test pattern generation from days to hours

Mountain View, CA. Synopsys Inc. on Tuesday announced its next-generation ATPG and diagnostics solution, TetraMAX II, incorporating the innovative test engines unveiled at the International Test ...
Electronic Design

A flexible flow for inserting embedded compression logic in RTL

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...