GitHub

SystemVerilog Functional Coverage for RISC-V ISA

This project is a work in progress (started in early 2022) to provide the RISC-V Verification ecosystem and users an immediate solution to SystemVerilog Functional Coverage for the RISC-V ISA. The ...
IEEE

Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD

Abstract: In recent years, considerable research has focused on the use of custom hardware to accelerate deep learning on edge devices. However, the end-to-end flow of deep learning includes ...
IEEE

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore

Abstract: Existing tiled manycore architectures propose to convert abundant silicon resources into general-purpose parallel processors with unmatched computational density and programmability. However ...