About a dozen years ago, the world of test had reached an economic impasse: most digital designs had become sufficiently complex that standard scan testing techniques were no longer cost-effective.

Part of the Synopsys synthesis-based test platform and embedded in Design Compiler RTL synthesis, DFTMAX Ultra delivers up to 3X higher compression to enable testing of several die in parallel and to ...

As IC design sizes continue to double every 18 to 24 months, those charged with testing the finished product are challenged on multiple fronts. Test-data volume and testing time are expanding, while ...

Test compression sounds like magic. Read on to learn how this trick is done. Large, complex ICs are viable because their design meets test as well as functional requirements. Design for test (DFT) was ...