IEEE

A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip ...

Abstract: This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip ...
GitHub

Outlier-Safe Pre-Training

Quantization plays a crucial role in deploying Large Language Models (LLMs) in resource-constrained environments. However, the presence of outlier features significantly hinders low-bit quantization.
IEEE

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator

Abstract: This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power ...