IEEE

Design of high-precision FFT based on VHDL and analysis of code coverage

Abstract: This paper uses structured design to implement the floating-FFT by VHDL with ISE5.3 and simulates it by ModelSim. The data pathways in this project are in the form of 32-bit single precision ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
GitHub

HTL8254 82C54 Compatible Programmable Interval Timer IP core

The HTL8254 IP core is written in vendor neutral VHDL and as such can be simulated by any simulation tool. The testbench however uses Siemens’ Modelsim SignalSpy in order to provide a non-intrusive ...
GitHub

A VHDL parser for syntax highlighting.

Neovim, using nvim-treesitter and a Tokyo Night colour scheme: Neovim, using nvim-treesitter and a One Dark colour scheme: If you'd like your favourite colour scheme to be listed here, issue a PR with ...
IEEE

A fast FPGA based architecture for computation of square root and Inverse Square Root

Abstract: This study aims to design a fast FPGA based system for computation of the Square Root and Inverse Square Root values using modified Quake's algorithm. In this work, new seven magic numbers ...