IEEE

A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre ...

Abstract: This article presents a compact 13-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) designed to enhance energy efficiency under various comparator input ...
IEEE

A 14-bit Pipelined-SAR ADC With Offset and Bit-Weight Calibration Techniques

Abstract: This work presents a 14-bit 100 MS/s Pipelined Successive-Approximation-Register (SAR) ADC in a 28nm CMOS process. The proposed calibration technique ...